Staff Machine Learning ASIC Design Engineer
Description For Staff Machine Learning ASIC Design Engineer
Qualcomm, the world's leading developer of next-generation wireless and multimedia technology, is seeking a Staff Machine Learning ASIC Design Engineer to join their team in Toronto, Canada. This role combines cutting-edge machine learning hardware development with ASIC design expertise. The position requires a seasoned professional with 5+ years of experience who will be responsible for developing micro-architecture specifications, RTL design optimization, and working with verification teams. The ideal candidate will have strong experience in Verilog/System Verilog RTL, machine learning hardware development, and various design tools and protocols. Qualcomm offers comprehensive benefits including health coverage, professional development opportunities, and wellbeing programs. This is an opportunity to work with leading technology experts and contribute to world-changing innovations in AI and hardware design. The role demands strong technical expertise combined with excellent communication and collaboration skills, offering a chance to work on next-generation AI/ML hardware IP solutions.
Responsibilities For Staff Machine Learning ASIC Design Engineer
- Develop Micro-Architecture and specification based on high level design requirements
- Develop RTL design that meets required performance and is optimized for Area and Power
- Integrate pre-verified sub-IPs to build up larger functionality
- Flow bring up and report analysis for Linting, RTL Synthesis, CLP, CDC
- Work closely with verification team to define testplan, debug regression, analyze coverage reports
- Develop SVA assertions for white box verification for formal verification
- Effective communication across teams, multitasking and well-planned execution of the tasks
Requirements For Staff Machine Learning ASIC Design Engineer
- Bachelor's degree in Science, Engineering, or related field and 4+ years of experience
- Prior experience delivering Verilog and System Verilog RTL
- Strong communication (written and verbal), collaboration, and specification skills
- Experience with simulation and code coverage tools
- Knowledge of clock domain crossing and reset architecture
- Experience with Machine Learning HW development
- Legally permitted to work on-site in Canada
- 5+ years of ASIC design, verification, or related work experience
Benefits For Staff Machine Learning ASIC Design Engineer
- World-class health coverage for employees and eligible dependents
- Financial planning and security programs
- Emotional/mental health support
- Wellbeing programs and resources
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
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