Staff R&D Design Technology Integration Engineer (WLP, Bump, Die Sort)
Description For Staff R&D Design Technology Integration Engineer (WLP, Bump, Die Sort)
Join Qualcomm's elite team focused on RF Front End Modules for Cellular and Wireless Data markets. As a Staff R&D Design Technology Integration Engineer, you'll be part of the Business Unit Engineering organization, working directly with multiple product development teams. This role requires a senior technical specialist who can provide leadership in developing new technology platforms using expertise in materials, device physics, and processes. You'll work in a dynamic, fast-paced environment, supporting advanced technologies for backend interconnect and packaging while collaborating with global teams. The position offers comprehensive benefits, professional growth opportunities, and the chance to work with industry-leading experts. Qualcomm's commitment to innovation and inclusive culture makes it an ideal place for those seeking to make a significant impact in wireless technology development.
Responsibilities For Staff R&D Design Technology Integration Engineer (WLP, Bump, Die Sort)
- Support development of advanced technologies for Si/GaAs backend interconnect and packaging
- Monitor and improve existing processes for yield, quality, and throughput
- Interface with foundries and OSATs for project management
- Lead technology integration into products and perform technical risk assessment
- Work cross-functionally with Design, Device process development, and global NPI teams
- Participate in value engineering and cost reduction plans
- Ensure product readiness for ramp and protect product integrity
Requirements For Staff R&D Design Technology Integration Engineer (WLP, Bump, Die Sort)
- Master's Degree or equivalent in Mechanical/Materials/Chemical Engineering (PhD Preferred)
- 10+ years of experience in electronics packaging, especially RF module industry
- 5+ years direct experience in process engineering, product integration or quality management
- Solid understanding of Semiconductor packaging materials and processes
- Knowledge of packaging industry standards (IPC, JEDEC, IEEE, ISO, ANSI)
- Understanding of package/product qualification and reliability methods
- Familiarity with PCB design and layout tools
- Understanding of statistics and control methodology
- Excellent communication skills
- Willingness to travel internationally
Benefits For Staff R&D Design Technology Integration Engineer (WLP, Bump, Die Sort)
- World-class health coverage for employees and dependents
- Financial planning and future security programs
- Mental health and emotional support resources
- Comprehensive wellbeing programs
- Tuition reimbursement
- Mentorship programs
- Continuous learning and development programs
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