Validation Engineer with DDR Familiarity

Leading technology innovator that pushes boundaries to enable next-generation experiences and drives communication and data processing transformation.
$140,000 - $210,000
Embedded
Senior Software Engineer
In-Person
5,000+ Employees
4+ years of experience
Enterprise SaaS · Hardware

Description For Validation Engineer with DDR Familiarity

Qualcomm Technologies, Inc., a leading technology innovator, is seeking a Validation Engineer with DDR Familiarity to join their Silicon Validation team. This role is part of the central SoC digital hardware organization responsible for ensuring overall SoC silicon quality. The position offers an exciting opportunity to work with cutting-edge technology and collaborate with architects, designers, verification engineers, and software engineers.

The role focuses on SOC validation in both pre-silicon emulation and post-silicon regression, with specific emphasis on DDR-related debugging and validation. The successful candidate will work with advanced memory technologies including RDIMM, LRDIMM, HBM3, HBM4, CXL, DDR5, and DDR6, while utilizing various debug tools and methodologies.

Qualcomm offers a comprehensive compensation package, including a competitive base salary range of $140,000 to $210,000, annual bonuses, and RSU grants. The company provides excellent benefits including medical, dental, vision coverage, 401k programs, and educational support. This position is based in San Diego, California, offering the opportunity to work at one of the world's leading semiconductor companies.

The ideal candidate should possess strong technical skills in hardware debugging, familiarity with DDR interfaces and JEDEC specifications, and experience with various testing and validation methodologies. The role requires a minimum of 4 years of experience with a Bachelor's degree (or equivalent combinations with advanced degrees) in Science, Engineering, or related fields.

Working at Qualcomm means being part of a team that drives innovation in mobile technologies, IoT, and next-generation computing. The company culture promotes collaboration, continuous learning, and professional growth, making it an ideal environment for engineers looking to advance their careers in hardware validation and testing.

Last updated 3 days ago

Responsibilities For Validation Engineer with DDR Familiarity

  • SOC validation in pre-silicon emulation and post-silicon regression
  • DDR related debug
  • Regression and PVT testing
  • Emulation Build Validation
  • Post-Si test execution and data review
  • Hardware debug and validation

Requirements For Validation Engineer with DDR Familiarity

  • Bachelor's degree in Science, Engineering, or related field with 4+ years experience, or Master's with 3+ years, or PhD with 2+ years
  • Familiarity with DDR interface, JEDEC spec, bus level view of transactions
  • Experience with Memory Analyzer, Logic Analyzer, DDR trace decoding and post processing
  • Familiar with RDIMM, LRDIMM, HBM3, HBM4, CXL, DDR5, DDR6
  • Potency in reading C code, understanding code flow, code manipulation
  • Proven track record of hardware debug
  • Experience with debug tools including JTAG and kernel debuggers
  • Lauterbach experience preferred

Benefits For Validation Engineer with DDR Familiarity

401k
Medical Insurance
Dental Insurance
Vision Insurance
Education Budget
  • Competitive annual discretionary bonus program
  • Annual RSU grants
  • Comprehensive health benefits
  • 401k program
  • Educational support

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