Rivos is developing accelerator designs for server compute silicon, focusing on performance optimization and validation.

Rivos is seeking a Senior Post-Silicon Performance Validation Engineer to join their Accelerator Performance team. This role is crucial for validating and optimizing the performance of their server compute silicon solutions.

The position offers an exciting opportunity to work at the intersection of hardware and AI/ML, focusing on performance validation of cutting-edge accelerator designs. You'll be responsible for analyzing and optimizing workload performance, particularly in data analytics, graph algorithms, and AI/ML applications.

As a key member of the team, you'll collaborate across multiple departments, including design, architecture, systems, and software teams, to ensure optimal performance for enterprise customer use-cases. The role involves hands-on work with silicon performance measurements, system-level debugging, and infrastructure automation.

The ideal candidate brings 5+ years of experience in SoC validation, strong programming skills in Python and C++, and deep familiarity with LLM/ML workloads. You should be comfortable with performance benchmarking tools like MLPerf and have a proven track record of working in cross-functional teams.

This hybrid position offers the flexibility to work from various locations including Santa Clara, Austin, Portland, Fort Collins, or HsinChu Taiwan. You'll be part of a company that's pushing the boundaries of accelerator design and performance optimization, with a direct impact on next-generation computing solutions.

The role requires both technical expertise and soft skills, including strong communication abilities, technical documentation skills, and the initiative to drive deliverables independently. You'll have the opportunity to influence product development through your performance analysis and optimization work.

Join Rivos to be part of a team that's advancing the state of the art in silicon accelerator technology, working on challenging problems at the forefront of hardware performance optimization.

Senior hardware engineering role focused on post-silicon performance validation for accelerator designs, requiring expertise in performance analysis and optimization.

Accelerator Post-Silicon Performance Validation Engineer

Rivos is a company focused on SOC design and development, specializing in advanced silicon engineering.

Rivos is seeking a Senior Silicon Bringup and Validation Engineer to join their team and lead critical initiatives in SOC design validation. This role is integral to the company's mission of developing cutting-edge SOC solutions, focusing on key components such as Power Management, DDR/HBM, PCIe, CPU, and data accelerator systems.

The position offers an opportunity to work at the intersection of hardware and software, requiring deep technical expertise in SOC design, including physical design, logic, performance, and power management. As a technical lead, you'll be responsible for bringing up and validating complex SOC subsystems, developing and executing comprehensive validation plans, and ensuring product requirements are met.

You'll lead a team in designing and implementing subsystem silicon bringup plans, collaborating across multiple disciplines including design, architecture, firmware, and software teams. The role involves significant interaction with vendors and partners, requiring strong communication and leadership skills.

This is an ideal position for experienced engineers with a strong background in silicon validation, verification methodologies, and programming skills in C/C++ and Python. The role demands both technical depth and leadership capabilities, offering the opportunity to drive innovation in SOC design and validation methodologies.

Working at Rivos means being part of a team that's pushing the boundaries of silicon engineering, with opportunities to influence the direction of next-generation SOC designs. The position requires on-site presence and offers the chance to work with state-of-the-art technology and tools in silicon development.

Senior Silicon Bringup and Validation Engineer role at Rivos, leading SOC subsystem validation and team coordination for next-generation silicon development.

Silicon Bringup and Validation Engineer

Cutting-edge and well-funded hardware startup in Silicon Valley reimagining silicon and creating computing platforms to transform the industry with advanced technologies.

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Logic Equivalence Check (LEC) Engineer at Rivos. Our mission is to reimagine silicon and create computing platforms that will transform the industry with the most advanced technologies. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency, and scalability.

As an LEC Engineer, you will be responsible for building and automating formal verification flow and supporting multiple design teams to consolidate resolutions. Your role will involve developing and improving existing flow for logical equivalent checks, working with ABORT/NEQ debugging processes, and using logical equivalence tools such as Conformal LEC and/or Formality.

Key responsibilities include:
- Collaborating with tool vendors for tool issues debugging and resolving
- Working with cross-functional RTL/PD/DFT teams to develop custom solutions
- Developing and maintaining in-house CAD tools and flow
- Proficiency in programming languages such as TCL, Python, and Perl

Additional valuable experience includes:
- Conformal ECO/Formality ECO
- Conformal Lowpower/VCLP
- Low Power implementation flows (UPF)
- Physical Synthesis/PNR and DFT implementation

We offer a fun, creative, and flexible work environment with a shared vision to build products that will change the world. Join us in pushing the boundaries of silicon technology and making a significant impact in the industry.

Required Education:
- BS (preferred in EE) plus 8 years of experience, or
- MS (preferred in EE) plus 5 years of experience

If you're passionate about hardware engineering, formal verification, and want to be part of a team creating next-generation computing platforms, we encourage you to apply for this exciting opportunity at Rivos.

Join Rivos as a Logic Equivalence Check (LEC) Engineer to develop and improve formal verification flows for cutting-edge silicon designs.

Logic Equivalence Check (LEC) Engineer

Rivos is a well-funded, cutting-edge hardware startup in Silicon Valley reimagining silicon and creating accelerated computing platforms.

Join Rivos, a well-funded, cutting-edge hardware startup in Silicon Valley, as an Accelerator Microarchitecture Performance Modeling Engineer. Our mission is to reimagine silicon and create accelerated computing platforms that will transform the industry.

In this role, you'll have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy-efficiency, programmability, and scalability. Your responsibilities will include functional and cycle-accurate simulator development, architectural and microarchitectural design-space exploration for programmable accelerators, as well as analysis and optimization of modern, highly-parallel applications.

You'll explore many adjacent areas of research and engineering, cross-cutting many levels of abstraction that must be scaled when building computing machinery - ISA design, application software, compiler optimization, RTL design, RTL correlation, design verification, test writing, and power/area analysis.

We offer a fun, creative, collaborative, and flexible work environment where you can contribute to our vision of building server-class compute machines that fulfill the promise and potential of hardware-software co-design while learning every day.

Key responsibilities include:
- Developing functional and timing simulators in C++ for Data Parallel Accelerator cores
- Conducting performance analysis and design space exploration
- Influencing design choices based on experiments and studies
- Developing and debugging performance tests
- Ensuring RTL design meets performance targets
- Analyzing workloads in machine learning, data analytics, and graph analytics

Requirements:
- In-depth knowledge of CPU/GPU Computer Architecture and Microarchitecture
- Excellent C/C++ coding skills
- Strong understanding of Machine Learning workloads and benchmarks
- Knowledge of SIMT processing, cache and memory hierarchies
- Experience with performance modeling and improvement concepts
- Ability to work well in a team and communicate effectively

This position offers a unique opportunity to shape the future of accelerated computing platforms while working with cutting-edge technology and a talented team. Join us in our mission to transform the industry through innovative silicon design and hardware-software co-design.

Join Rivos as an Accelerator Microarchitecture Performance Modeling Engineer to develop cutting-edge hardware for accelerated computing platforms.

Accelerator Microarchitecture Performance Modeling Engineer

Rivos is developing secure-by-design RISC-V based systems and evolving the RISC-V ecosystem.

Rivos is seeking a Security Infrastructure Engineer to join their team working on software, firmware, and hardware to evolve the RISC-V ecosystem and build secure-by-design RISC-V based systems. The security team is responsible for defining external and internal interfaces for secure provisioning and trusted computing base (TCB) updates of their SOC and platforms. They are building security infrastructure services to support secure device provisioning and lifecycle management for the SOC-Integrated Root of Trust (RoT), and manage trusted elements of the platform.

The role involves designing, developing, and deploying security infrastructure services for key management, manufacturing provisioning, certificate authority, and code signing. The ideal candidate will be a full stack developer with fault-tolerant systems experience and a strong security background. They should have experience with hardware security modules (HSM), integrating remote systems with automatic test equipment (ATE), and operational experience in deploying and maintaining security infrastructure.

Rivos is a proponent of open source software and open hardware, contributing improvements to projects they use. This position offers the opportunity to work on cutting-edge RISC-V technology and contribute to the development of secure computing platforms. The role requires a blend of technical expertise in security, software development, and systems integration, making it an exciting opportunity for those passionate about secure computing and emerging technologies.

Security Infrastructure Engineer role at Rivos, focusing on RISC-V based secure systems and infrastructure services.

Security Infrastructure Engineer

Rivos is a technology company specializing in silicon engineering and AI acceleration.

Rivos is a cutting-edge technology company specializing in silicon engineering and AI acceleration. They are currently hiring for various positions in silicon engineering, including CPU design, SOC architecture, and AI software engineering. The company offers a range of opportunities across different locations, including Santa Clara, Austin, Portland, and Fort Collins in the US, as well as international locations like Bangalore, India, and HsinChu, Taiwan. 

Rivos is looking for experienced professionals in areas such as CPU microarchitecture, logic design, verification, physical design, and AI software development. They also have positions in SOC design, interconnect architecture, and security infrastructure.

The company seems to be working on advanced technologies in the field of AI acceleration and custom silicon design. They offer both full-time positions and internships, with many roles allowing for hybrid work arrangements.

Joining Rivos would provide an opportunity to work on cutting-edge hardware and software technologies in the AI and silicon space. The company appears to be growing rapidly and offers positions across various levels of experience, from entry-level to senior roles.

For those interested in pushing the boundaries of AI hardware and software co-design, Rivos presents an exciting career opportunity. The diverse range of positions available suggests a comprehensive approach to chip design and AI acceleration, making it an attractive option for professionals in the semiconductor and AI industries.

Rivos is hiring for various silicon engineering positions, focusing on AI acceleration and custom chip design.

Rivos Engineering Jobs

Rivos is developing accelerator designs for server compute silicon, focusing on performance optimization and validation.