Design Verification Engineer (Silicon Engineering)
Description For Design Verification Engineer (Silicon Engineering)
SpaceX, founded with the vision of exploring the stars, is at the forefront of space technology development. Their ultimate goal is to enable human life on Mars. Currently, they're leveraging their expertise in rockets and spacecraft to deploy Starlink, the world's largest satellite constellation providing fast, reliable internet globally.
As a Design Verification Engineer (Silicon Engineering) at SpaceX, you'll be part of the team developing cutting-edge FPGAs and ASICs for space and ground infrastructures. Your work will directly contribute to expanding the performance and capabilities of the Starlink network, bringing connectivity to previously underserved areas.
You'll work alongside world-class cross-disciplinary teams, developing test plans, creating test harnesses, and implementing verification methodologies. Your responsibilities will include digital ASIC and FPGA verification, developing SystemVerilog testbench infrastructure, and automating test case generation using Python and MATLAB.
This role requires a bachelor's degree in electrical engineering, computer science, or computer engineering, with 2+ years of experience in design verification and test bench development. Preferred skills include an advanced degree, experience with UVM, strong object-oriented programming knowledge, and expertise in developing test plans and implementing coverage models.
Join SpaceX to be part of a dynamic team pushing the boundaries of space technology and global connectivity. You'll have the opportunity to work on projects that have a real-world impact, bringing internet access to millions worldwide and contributing to the goal of making humanity a multi-planetary species.
Responsibilities For Design Verification Engineer (Silicon Engineering)
- Responsible for digital ASIC and/or FPGA verification at block and system level
- Write and review test plans, develop test harnesses and test sequences
- Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
- Responsible for test plan execution, running regressions, code and functional coverage closure
- Automate test case generation by using Python and MATLAB programs
- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
- Be a hands-on self-starter who can execute the steps required to fully verify complex digital designs
Requirements For Design Verification Engineer (Silicon Engineering)
- Bachelor's degree in electrical engineering, computer science or computer engineering
- 2+ years of experience with design verification and test bench development
- Strong object-oriented programming knowledge
- Strong problem-solving and coding skills
- Ability to work in a dynamic environment with changing needs and requirements
- Must be willing to work extended hours and weekends as needed
- Must be a U.S. citizen, permanent resident, refugee, or asylee due to ITAR requirements
Benefits For Design Verification Engineer (Silicon Engineering)
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks of paid vacation
- 10 or more paid holidays per year
- 5 days of sick leave per year for exempt employees
- Long-term incentives (company stock, stock options, or long-term cash awards)
- Potential discretionary bonuses
- Employee Stock Purchase Plan
- Various discounts and perks
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