Design Verification Engineer (Silicon Engineering)

SpaceX develops technologies for space exploration and Starlink, the world's largest satellite constellation providing global broadband internet.
$130,000 - $180,000
Embedded
Mid-Level Software Engineer
In-Person
2+ years of experience
Space · Enterprise SaaS

Description For Design Verification Engineer (Silicon Engineering)

SpaceX, a pioneering space technology company, is seeking a Design Verification Engineer to join their Starlink team. This role is crucial in developing next-generation FPGAs and ASICs for both space and ground infrastructure, directly contributing to the world's largest satellite constellation providing global broadband internet.

The position offers an exciting opportunity to work alongside world-class cross-disciplinary teams, developing cutting-edge solutions that expand the performance and capabilities of the Starlink network. You'll be responsible for digital ASIC and FPGA verification, working with SystemVerilog, UVM, and various testing methodologies.

This is an ideal role for someone with a strong background in electrical engineering or computer science, with experience in design verification and test bench development. The position offers comprehensive benefits including equity, medical coverage, and 401(k), along with the unique opportunity to work on technology that's literally changing the world.

The role combines technical expertise with practical implementation, requiring someone who can handle both detailed verification work and broader system-level thinking. You'll be part of SpaceX's mission to make humanity a multi-planetary species while helping provide internet access to underserved areas of the world.

Working at SpaceX means being part of a team that's pushing the boundaries of what's possible in space technology and telecommunications. The company culture emphasizes innovation, rapid iteration, and direct impact on products that are revolutionizing both space exploration and global internet connectivity.

Last updated a month ago

Responsibilities For Design Verification Engineer (Silicon Engineering)

  • Responsible for digital ASIC and/or FPGA verification at block and system level
  • Write and review test plans, develop test harnesses and test sequences
  • Develop SystemVerilog testbench infrastructure for testing designs, including DSP blocks
  • Responsible for test plan execution, running regressions, code and functional coverage closure
  • Automate test case generation using Python and MATLAB programs
  • Contribute towards pre-silicon verification, chip bring-up and post-silicon validation

Requirements For Design Verification Engineer (Silicon Engineering)

Python
  • Bachelor's degree in electrical engineering, computer science or computer engineering
  • 2+ years of experience with design verification and test bench development
  • Must be willing to work extended hours and weekends as needed
  • Must be a U.S. citizen, permanent resident, refugee, or asylee (ITAR requirements)

Benefits For Design Verification Engineer (Silicon Engineering)

Medical Insurance
Dental Insurance
Vision Insurance
401k
Equity
Parental Leave
  • Company stock and stock options
  • Long-term cash awards
  • Potential discretionary bonuses
  • Employee Stock Purchase Plan
  • Comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • Short & long-term disability insurance
  • Life insurance
  • Paid parental leave
  • 3 weeks paid vacation
  • 10+ paid holidays per year
  • 5 days sick leave per year

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