SOC/ASIC Timing Signoff & Front-End Implementation Engineer
Description For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
SpaceX, a pioneering space technology company, is seeking a SOC/ASIC Timing Signoff & Front-End Implementation Engineer to join their Silicon Engineering team. This role is crucial in developing cutting-edge ASICs for both space and ground infrastructure, particularly supporting the Starlink project - the world's largest satellite constellation providing global internet coverage.
The position offers an opportunity to work alongside world-class cross-disciplinary teams, including systems, firmware, architecture, design, validation, and product engineering specialists. You'll be at the forefront of developing advanced timing/noise signoff flows, defining timing signoff criteria, and implementing sophisticated engineering solutions that directly impact the performance and capabilities of the Starlink network.
This is an ideal role for someone with strong technical expertise in static timing analysis and SOC design, combined with excellent scripting skills and experience with deep sub-micron FinFET technology. The position offers competitive compensation ($120,000-$170,000) and comprehensive benefits, including equity opportunities and healthcare coverage.
Working at SpaceX means contributing to the ambitious goal of enabling human life on Mars while solving immediate challenges in global connectivity. The role requires ITAR compliance and offers the unique opportunity to work on technology that's literally changing both Earth and space exploration.
Responsibilities For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Develop/support automated block and full chip level advanced timing/noise signoff flows
- Define block and full chip timing signoff criterion, methodology, constraints, modes and scenarios
- Develop/support signoff STA timing/power optimization engineering change order flows
- Work with cross-disciplinary teams to address design challenges
- Generate block timing budgets, clock and I/O context files
- Debug and drive fixing of constraint correlation issues
- Develop clock network simulation and jitter analysis methodologies
Requirements For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Bachelor's degree in electrical engineering, computer engineering or computer science
- Experience in static timing analysis and/or timing closure of high-performance SOC designs
- Experience with deep sub-micron FinFET technology nodes
- Experience with industry standard STA and Noise/Signal integrity analysis tools
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile)
- Must be willing to travel when needed (typically <10%)
- Must be U.S. citizen, permanent resident, refugee, or asylee (ITAR requirements)
Benefits For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Company stock or stock options
- Long-term cash awards
- Discretionary bonuses
- Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation
- 10+ paid holidays per year
- 5 days sick leave per year
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