SOC/ASIC Timing Signoff & Front-End Implementation Engineer
Description For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
SpaceX, a pioneering space technology company, is seeking a Senior SOC/ASIC Timing Signoff & Front-End Implementation Engineer to join their Silicon Engineering team. This role is crucial in developing cutting-edge ASICs for both space and ground infrastructure supporting the Starlink satellite constellation, the world's largest satellite internet system.
The position offers an unique opportunity to work on hardware that will literally reach for the stars, as part of SpaceX's mission to make humanity a multi-planetary species. You'll be working alongside world-class cross-disciplinary teams, developing solutions that will expand the performance and capabilities of the Starlink network, bringing reliable internet connectivity to previously underserved areas around the globe.
As a senior engineer in this role, you'll be responsible for developing and supporting advanced timing/noise signoff flows, defining critical methodologies for chip timing signoff, and working with various teams to address complex design challenges. The role requires expertise in static timing analysis, deep sub-micron FinFET technology, and extensive experience with industry-standard tools and methodologies.
The compensation package is highly competitive, ranging from $120,000 to $170,000 per year, complemented by an impressive benefits package including equity opportunities, comprehensive healthcare, and various other perks. This is an ideal opportunity for a skilled engineer who wants to contribute to groundbreaking space technology while working with some of the industry's best minds.
The position requires ITAR compliance, meaning candidates must be U.S. citizens, permanent residents, refugees, or asylees. The role may require occasional travel (less than 10%) and the flexibility to work extended hours when needed to meet critical deadlines. If you're passionate about pushing the boundaries of technology and want to be part of a team that's literally changing the world's connectivity landscape, this role at SpaceX could be your next career milestone.
Responsibilities For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Develop/support automated block and full chip level advanced timing/noise signoff flows
- Define block and full chip timing signoff criterion, methodology, constraints, modes and scenarios
- Develop/support signoff STA timing/power optimization engineering change order flows
- Work with systems and architecture teams to address design challenges
- Generate block timing budgets, clock and I/O context files
- Debug and drive fixing of constraint correlation issues
- Develop clock network simulation and jitter analysis methodologies
Requirements For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Bachelor's degree in electrical engineering, computer engineering or computer science
- Experience in static timing analysis and/or timing closure of high-performance SOC designs
- Full chip and block level STA tapeout experience
- Knowledge of deep sub-micron FinFET technology nodes
- Experience with memories, I/Os, Analog IPs, SerDes, DDR
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile)
- Must be willing to travel when needed (typically <10%)
- Must be a U.S. citizen, permanent resident, refugee, or asylee (ITAR requirements)
Benefits For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Company stock and stock options
- Long-term cash awards
- Discretionary bonuses
- Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation
- 10+ paid holidays per year
- 5 days sick leave per year
Jobs Related To SpaceX SOC/ASIC Timing Signoff & Front-End Implementation Engineer
