SOC/ASIC Timing Signoff & Front-End Implementation Engineer
Description For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
SpaceX, a pioneering space technology company, is revolutionizing space exploration with the ultimate goal of enabling human life on Mars. As part of their groundbreaking Starlink project, which provides high-speed internet globally through the world's largest satellite constellation, they're seeking a talented SOC/ASIC Timing Signoff & Front-End Implementation Engineer.
This role offers a unique opportunity to work on cutting-edge ASIC development for both space and ground infrastructure, directly contributing to making internet connectivity available in previously underserved areas worldwide. You'll be working alongside world-class cross-disciplinary teams, including systems, firmware, architecture, design, and validation experts.
The position requires expertise in static timing analysis, chip-level timing signoff, and deep sub-micron FinFET technology. You'll be responsible for developing and supporting automated timing/noise signoff flows, defining timing signoff criteria, and working on power optimization. The role demands strong technical skills, including experience with industry-standard STA tools and excellent scripting abilities.
SpaceX offers a comprehensive benefits package, including competitive base salary ranging from $120,000 to $170,000, equity opportunities, medical benefits, and retirement plans. The company's dynamic environment and mission-driven culture provide an exciting opportunity to contribute to revolutionary space technology while working with some of the industry's brightest minds.
This position requires ITAR compliance (U.S. citizen, permanent resident, refugee, or asylee) and occasional travel. If you're passionate about pushing the boundaries of technology and want to be part of a team that's literally reaching for the stars, this role at SpaceX could be your next career milestone.
Responsibilities For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Develop/support automated block and full chip level advanced timing/noise signoff flows
- Define block and full chip timing signoff criterion and methodology
- Develop signoff STA timing/power optimization engineering change order flows
- Work with cross-functional teams to address design challenges
- Generate block timing budgets, clock and I/O context files
- Debug and fix constraint correlation issues
- Develop clock network simulation and jitter analysis methodologies
Requirements For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Bachelor's degree in electrical engineering, computer engineering or computer science
- Experience in static timing analysis and timing closure of high-performance SOC designs
- Experience with deep sub-micron FinFET technology nodes
- Experience with industry standard STA and Noise/Signal integrity analysis tools
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile)
- Must be willing to travel when needed (typically <10%)
- Must be U.S. citizen, permanent resident, refugee, or asylee (ITAR requirements)
Benefits For SOC/ASIC Timing Signoff & Front-End Implementation Engineer
- Company stock or stock options
- Long-term cash awards
- Discretionary bonuses
- Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation
- 10+ paid holidays per year
- 5 days sick leave per year
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