Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX develops technologies for space exploration, including rockets, spacecraft, and Starlink - the world's largest satellite constellation for broadband internet.
$160,000 - $220,000
Embedded
Senior Software Engineer
In-Person
1,000 - 5,000 Employees
5+ years of experience
Space

Description For Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX, a pioneering space technology company, is seeking a Senior ASIC Design Engineer to join their Starlink team. This role is crucial in developing next-generation FPGAs and ASICs for both space and ground infrastructure that powers the world's largest satellite constellation. The position offers an opportunity to work on cutting-edge technology that's bringing internet connectivity to previously underserved areas globally.

The ideal candidate will join a world-class cross-disciplinary team, working on complex system-on-chip designs and implementations. You'll be responsible for developing sophisticated digital solutions that directly impact the performance and capabilities of the Starlink network. This role requires expertise in ASIC/FPGA design, system integration, and various EDA tools.

SpaceX offers a comprehensive benefits package including equity opportunities, medical benefits, and retirement plans. The company's mission to enable human life on Mars and revolutionize space technology provides an exciting backdrop for engineering challenges. This role offers the unique opportunity to contribute to space technology advancement while solving real-world connectivity challenges.

The position requires strong technical skills in digital design, verification, and implementation, combined with the ability to work in a dynamic, fast-paced environment. You'll be part of a team that values innovation, problem-solving, and the pursuit of ambitious goals in space technology.

Last updated 6 days ago

Responsibilities For Sr. ASIC Design Engineer (Silicon Engineering)

  • Design digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks
  • Analyze architectural trade-offs based on features, performance requirements and system limitations
  • Define micro-architecture, implement or integrates design blocks using Verilog/SystemVerilog
  • Participate in all phases of ASIC and/or FPGA design flow
  • Participate in silicon bring-up for blocks owned

Requirements For Sr. ASIC Design Engineer (Silicon Engineering)

Python
Linux
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of experience working with ASICs or FPGAs
  • Experience with EDA tools and HDL simulators
  • Excellent scripting skills (csh/bash, Perl, Python etc.)
  • Experience with standard bus protocols
  • Must be a U.S. citizen, permanent resident, refugee, or asylee (ITAR requirements)

Benefits For Sr. ASIC Design Engineer (Silicon Engineering)

Medical Insurance
Dental Insurance
Vision Insurance
401k
Equity
Parental Leave
  • Company stock or stock options
  • Long-term cash awards
  • Discretionary bonuses
  • Employee Stock Purchase Plan
  • Comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • Short & long-term disability insurance
  • Life insurance
  • Paid parental leave
  • 3 weeks paid vacation
  • 10+ paid holidays per year
  • 5 days sick leave per year

Interested in this job?

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