Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX, a pioneering space exploration company, is seeking a Senior SOC/ASIC Physical Design Engineer to join their Silicon Engineering team in Sunnyvale, CA. This role is crucial in developing cutting-edge silicon solutions for both space and ground infrastructure, directly contributing to the Starlink project - the world's largest satellite constellation providing global internet access.

The position offers an exciting opportunity to work alongside world-class cross-disciplinary teams, focusing on developing next-generation silicon that will enable connectivity in previously underserved areas. The role combines advanced technical challenges in ASIC design with the meaningful impact of expanding global internet access through the Starlink network.

As a Sr. SOC/ASIC Physical Design Engineer, you'll be responsible for complex technical tasks including partition synthesis, physical implementation, and developing automation scripts for various implementation steps. The role requires strong expertise in ASIC/SOC RTL2GDSII physical design and signoff flows, along with deep knowledge of CMOS technology and circuit design principles.

The position offers competitive compensation ranging from $170,000 to $230,000 per year, along with comprehensive benefits including medical coverage, 401(k), stock options, and paid time off. This is an ideal opportunity for experienced engineers passionate about pushing the boundaries of silicon design while contributing to SpaceX's mission of making humanity a multi-planetary species.

The role requires a minimum of 5 years of industry experience and a bachelor's degree in a relevant field. The successful candidate will be a self-driven individual with strong technical skills and the ability to work in a dynamic environment. Given SpaceX's work in space technology, candidates must meet ITAR requirements and be authorized to work in the United States.