CPU Microarchitecture/RTL Engineer
Description For CPU Microarchitecture/RTL Engineer
Tenstorrent is at the forefront of AI technology innovation, developing cutting-edge solutions that are revolutionizing the computing industry. We are building high-performance RISC-V CPUs from the ground up, combining innovations in software models, compilers, platforms, networking, and semiconductors.
As a CPU Microarchitecture/RTL Engineer, you'll join a highly experienced team working on critical components of our high-performance CPU architecture. You'll be responsible for the RTL design and microarchitecture of the Load/Store unit, working with the latest RISC-V ISA technology. This role offers a unique opportunity to work on groundbreaking technology that's reshaping the AI computing landscape.
The position requires deep expertise in CPU architecture, with hands-on experience in RTL design, verification, and optimization. You'll be working with both industry-standard and open-source tools, collaborating across teams to deliver high-quality, performant solutions. The role demands a strong background in computer architecture, particularly in areas such as load/store engines, memory consistency, and MMU.
We offer a highly competitive compensation package ranging from $100k to $500k, including base and variable compensation. Our culture values collaboration, curiosity, and a commitment to solving hard problems. As part of our team, you'll have the opportunity to work with diverse, talented technologists who share a passion for AI and a deep desire to build the best AI platform possible.
The position offers flexibility with a hybrid work arrangement in either Santa Clara, CA or Austin, TX. Join us in our mission to redefine the computing paradigm and build the next generation of AI technology.
Responsibilities For CPU Microarchitecture/RTL Engineer
- RTL design and Microarchitecture of the Load/Store unit for high performance RISC-V ISA CPU
- RTL coding in Verilog using industry and open-source infrastructure
- Work with design, test and post silicon validation teams
- Drive trade-offs for logic working with performance, DV and physical design engineers
- Deploy innovative techniques for improving power, performance and area of the design
- Debug RTL/logic issues across various hierarchies
- Enhance RTL design environment, tools and infrastructure
Requirements For CPU Microarchitecture/RTL Engineer
- BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience
- Strong background in high performance OOO CPU microarchitecture
- Experience working on x86, ARM or RISC-V based CPU
- Architectural understanding of load/store engines, memory consistency, MMU, Interface protocols for Out of Order CPU
- Expertise in logic design and ability to evaluate functional, performance, timing and power
- Strong experience with hardware description languages, simulators, Synthesis and Power tools
- Expertise in microarchitecture definition and specification development
- Strong problem solving and debug skills
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