Design for Test (DFT) Engineer
Description For Design for Test (DFT) Engineer
Tenstorrent is at the forefront of AI technology innovation, developing cutting-edge solutions that are revolutionizing performance, usability, and cost efficiency in the AI computing space. The company has successfully developed a high-performance RISC-V CPU from the ground up and is focused on building the best AI platform possible.
As a Design for Test (DFT) Engineer, you'll be working on high-performance designs for industry-leading AI/ML architectures. This role involves all implementation aspects from RTL to tapeout for various IPs on the chip. You'll tackle challenges like reducing test cost while maintaining high coverage and facilitating debug and yield learnings while minimizing design intrusions.
The position offers an opportunity to work with a diverse team of highly experienced engineers across various ASIC domains. You'll be implementing DFT features, working with industry-standard tools, and supporting silicon bring-up and debug. The role requires expertise in advanced DFx techniques, finFET technologies, and a strong understanding of high-performance, low-power design fundamentals.
Working in a hybrid model from Bangalore, you'll be part of a company that values collaboration, curiosity, and a commitment to solving hard problems. Tenstorrent offers competitive compensation and benefits, making it an attractive opportunity for those passionate about pushing the boundaries of AI technology and hardware design.
The company welcomes candidates at various experience levels, with assessment during the interview process determining the appropriate level for offers. This is an excellent opportunity for someone looking to contribute to groundbreaking AI technology development while working with a team of talented technologists.
Responsibilities For Design for Test (DFT) Engineer
- Implementation of DFT features into RTL using verilog
- Understanding of DFT Architectures and micro-architectures
- ATPG and test coverage analysis using industry standard tools
- JTAG, Scan Compression, and ASST implementation
- Gate level simulation using Synopsys VCS and Verdi
- Support silicon bring-up and debug
- MBIST planning, implementation, and verification
- Support Test Engineering on planning, patterns, and debug
- Develop efficient DFx flows and methodology compatible with front end and physical design flows
Requirements For Design for Test (DFT) Engineer
- BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques
- DFx experience implementing in finFET technologies
- Experience with industry standard ATPG and DFx insertion CAD tools
- Familiarity with SystemVerilog and UVM
- Fluent in RTL coding for DFx logic
- Understanding of low-power design flows
- Good understanding of high-performance, low-power design fundamentals
- Knowledge of fault models
- Strong problem solving and debug skills
Benefits For Design for Test (DFT) Engineer
- Competitive compensation package
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