Fabric and Memory Subsystem Microarchitecture Engineer
Description For Fabric and Memory Subsystem Microarchitecture Engineer
Tenstorrent is at the forefront of AI technology, revolutionizing performance, usability, and cost-efficiency in the industry. As AI reshapes computing, we're developing solutions that unify innovations across software models, compilers, platforms, networking, and semiconductors. Our diverse team has created a high-performance RISC-V CPU from scratch, driven by a passion for AI and a commitment to building the best AI platform possible.
We're seeking an experienced engineer to focus on Fabric and Memory Subsystem microarchitecture and RTL for high-performance SOCs. You'll work on a server-class SoC fabric supporting cutting-edge data center designs. This hybrid role is based out of Toronto (ON), Boston (MA), or Austin (TX).
Key responsibilities include:
- Designing and developing Fabric and Memory subsystems from scratch for a high-performance CPU
- Creating RTL implementations in Verilog
- Collaborating with cross-functional teams
- Evaluating and integrating 3rd-party IP components
- Optimizing power, performance, and area (PPA)
- Conducting experiments with RTL and analyzing results
- Debugging complex RTL/logic issues
- Enhancing RTL design infrastructure and tools
Qualifications:
- BS/MS/PhD in EE/ECE/CE/CS with 5+ years of experience in Fabric or Memory subsystem design
- Extensive experience with CPU and GPU fabrics, including cache coherence protocols and memory ordering models
- Strong understanding of interconnect topologies and protocols
- Proven ability to optimize memory subsystems with CPU cores
- Experience with PPA trade-offs and relevant tools
- Expertise in hardware description languages and simulators
- Strong debugging and problem-solving skills
Tenstorrent offers competitive compensation and benefits, and is an equal opportunity employer. Note that due to U.S. Export Control laws, citizenship/permanent residency information may be required as a condition of employment.
Responsibilities For Fabric and Memory Subsystem Microarchitecture Engineer
- Design and develop the Fabric and Memory subsystems from scratch for a high-performance CPU
- Create RTL implementations in Verilog using both industry-standard tools and open-source infrastructure
- Collaborate with cross-functional teams, including design, test, and post-silicon validation
- Evaluate and integrate 3rd-party IP components into the subsystem
- Optimize power, performance, and area (PPA)
- Conduct experiments with RTL and analyze synthesis, timing, and power results
- Debug complex RTL/logic issues across different design hierarchies
- Enhance RTL design infrastructure and tools
Requirements For Fabric and Memory Subsystem Microarchitecture Engineer
- BS/MS/PhD in EE/ECE/CE/CS with 5+ years of experience in Fabric or Memory subsystem design
- Extensive experience with CPU and GPU fabrics, including cache coherence protocols and memory ordering models (e.g., MOESI)
- Strong understanding of interconnect topologies and protocols such as CHI, AXI, ACE, TileLink
- Proven ability to tightly couple memory subsystems with CPU cores
- Experience evaluating PPA trade-offs and working with synthesis, timing, and power tools
- Hands-on experience with hardware description languages (Verilog, SystemVerilog) and simulators like VCS, NC, and Verilator
- Expertise in microarchitecture definition and specification development for complex memory systems
- Strong debugging and problem-solving skills across hierarchical levels
Benefits For Fabric and Memory Subsystem Microarchitecture Engineer
- Competitive compensation package
- Benefits
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