L2/Shared Cache Verification Engineer
Description For L2/Shared Cache Verification Engineer
Tenstorrent, a pioneering company in AI technology, is revolutionizing the industry with cutting-edge solutions that unite innovations across software models, compilers, platforms, networking, and semiconductors. We're seeking an experienced L2/Shared Cache Verification Engineer to join our dynamic team in Bangalore.
The role focuses on developing and implementing verification strategies for our high-performance RISC-V CPU's L2/Shared Cache unit. You'll work at the intersection of hardware and software, collaborating with Architecture and RTL teams to ensure robust functionality and performance. This position requires deep expertise in CPU microarchitecture, particularly in cache systems and memory subsystems.
As a verification engineer, you'll be responsible for creating comprehensive verification plans, developing testbench components using SV, UVM, and C++, and driving verification efforts across pre-silicon, emulation, and post-silicon phases. The role demands strong technical skills in hardware description languages, simulation tools, and debugging capabilities.
We offer a collaborative environment where innovation thrives, and team members are encouraged to tackle complex technical challenges. Our competitive compensation package reflects our commitment to attracting top talent. This is an excellent opportunity for experienced engineers passionate about CPU architecture and verification to contribute to groundbreaking AI technology development.
Note: Due to U.S. Export Control regulations, citizenship/permanent residency status will be considered as a condition of employment, and a U.S. export license may be required for some candidates.
Responsibilities For L2/Shared Cache Verification Engineer
- Functional and performance verification of the L2/Shared Cache unit for high-performance CPU
- Develop detailed block level verification plans for L2/Shared Cache
- Design and develop reusable block level testbench components in SV, UVM and C++
- Develop random and directed stimulus for pre-silicon, emulation and post-silicon domain
- Evaluate and integrate open-source toolchains into the DV flow
- Develop DV environment, tools and infrastructure
- Work with design, test and post silicon validation teams
Requirements For L2/Shared Cache Verification Engineer
- BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
- Strong background in high performance OOO CPU microarchitecture
- Experience working on x86, ARM or RISCV based CPU
- Understanding of address translation, memory ordering, cache coherence protocols
- Experience debugging RTL and DV in simulation environment
- Proficiency in C++, SV, UVM and scripting languages
- Experience with hardware description languages (Verilog, VHDL)
- Strong problem solving and debug skills
Benefits For L2/Shared Cache Verification Engineer
- Competitive compensation package
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