Senior ASIC Design Engineer
Description For Senior ASIC Design Engineer
Tenstorrent is at the forefront of AI technology, revolutionizing performance, usability, and cost-efficiency in the industry. As AI reshapes computing, we're developing solutions that unite innovations across software models, compilers, platforms, networking, and semiconductors. Our team of diverse technologists has created a high-performance RISC-V CPU from scratch, driven by a shared passion for AI and a commitment to building the best AI platform possible.
We're seeking a skilled professional to join our high-profile project, designing and integrating multiple chiplets into a System-in-package. This role involves collaboration with external stakeholders and Tenstorrent experts worldwide. You'll be responsible for synthesis and place and route using industry-standard tools for high-speed CPU core design, with a focus on cutting-edge silicon technology (5nm and lower) and multi-GHz design.
Based in Tokyo, Japan, this position offers the opportunity to work with a global team, contribute to groundbreaking technology, and help refine our IP. We welcome candidates at various experience levels, with offers aligned to the appropriate level determined during the interview process.
Key responsibilities include performing all aspects of the design flow, developing strategies for reproducible design convergence, and mentoring junior engineers. The ideal candidate will have extensive experience in SoC/ASIC/GPU/CPU design flows, expertise in timing closure, and strong skills in scripting and communication.
Join Tenstorrent to be part of a collaborative, curious team committed to solving hard problems and shaping the future of AI computing. We offer competitive compensation and benefits, and we're an equal opportunity employer. Note that due to U.S. Export Control laws, citizenship/permanent residency information may be required as a condition of employment.
Responsibilities For Senior ASIC Design Engineer
- Synthesis and Place and Route using industry standard tools for high speed CPU core design
- Plan out resources, schedule, project PPA
- Develop strategies to deliver reproducible design convergence results
- Help to create and refine synthesis and PNR flow for the project team
- Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks and design closure
- Develop and recommend better design methodologies to enable better timing convergence
- Guide and mentor junior engineers
- PV convergence (including static timing and power analysis)
- Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
- Scripting in an interpreted language, minimum TCL in addition to at least one other
Requirements For Senior ASIC Design Engineer
- Bachelor, Master or PhD degree in electrical, computer engineering or computer science
- At least 10 years of relevant industry experience
- Experience with integrated circuit design tools (e.g. Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
- Experience with PV convergence, including static timing and power analysis
- Experience with chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise and electro-mitigation checks
- Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
- Strong experience in SoC/ASIC/GPU/CPU design flows on taped out designs
- Expertise in timing closure and block/chip levels and ECO flows
- Experience with scripting in an interpreted language (Python, TCL)
- Willingness to work with others in a highly complex decision space
- Skills at developing an implementation plan, monitoring key indicators and communicating resource needs, as well as scoping risk to deliver value on schedule
- Excellent verbal and written communication in English, and collaboration skills
Benefits For Senior ASIC Design Engineer
- Competitive compensation package and benefits
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