Sr Staff Engineer, PCIe & IO Subsystem Design

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems.

We are seeking an experienced engineer focused on PCIe & IO Subsystem design for high-performance CPUs. This role involves working on a server-class SoC and can be based out of Austin, TX; Santa Clara, CA; Boston, MA; or Toronto, Ontario.

Responsibilities:

• Design and development of the PCIe/IO subsystem unit for a high-performance CPU SoC from scratch, working closely with the Architecture and RTL teams.
• Develop detailed block-level design specifications and plans for a high-performance PCIe & IO Subsystem.
• Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers.
• Develop and optimize the PCIe/IO subsystem design to ensure seamless integration and high performance.
• Evaluate and integrate open-source toolchains into the design flow.
• Collaborate with the design, test, and post-silicon validation teams to ensure high-quality delivery of the PCIe/IO Subsystem.

Experience and Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of relevant experience.
• Strong background and experience with high-performance OOO CPU microarchitecture, particularly with IO subsystems and CPU interactions with PCIe & IO complexes.
• Experience designing PCIe/IO Subsystems for CPU or GPU-based systems, with knowledge of industry-standard protocols such as PCIe & CXL, as well as CHI, AXI, ACE, Tilelink, and CMN.
• Architectural understanding of PCIe ordering, non-coherent flows, IO-device memory flows, peer-to-peer, bifurcation, posted vs. non-posted transactions, etc.
• Significant experience debugging and optimizing RTL and design implementations in a simulation environment.
• Familiarity with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator).
• Strong problem-solving and debug skills across various levels of design hierarchies.
• Experience with C++, SV, UVM, and scripting languages.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.