Staff Design Verification Engineer - CPU Subsystem

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. We are seeking a Staff Design Verification Engineer for our CPU Subsystem team in Bengaluru, India. This role requires expertise in System Verilog and UVM methodologies, with responsibilities including defining verification plans, developing DV environments, and ensuring the quality of our IP solutions. The ideal candidate will have a strong background in functional verification at the RTL level, experience with Cache and NOC Interconnect verification, and knowledge of bus protocols like AXI and CHI. We offer a competitive compensation package and benefits, and value collaboration, curiosity, and a commitment to solving hard problems. Join our diverse team of technologists who have developed a high-performance RISC-V CPU from scratch and share a passion for AI and building the best AI platform possible.

Key Responsibilities:

• Define verification plans and develop DV environments independently in System Verilog (SV)/UVM
• Create and execute test plans for IP solutions
• Perform functional verification at the RTL level, including coverage analysis and improvement
• Develop Universal Verification Components (UVCs) from scratch
• Work with Cache and NOC Interconnect verification

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field
• Proven experience in DV and verification methodologies
• Strong proficiency in System Verilog and UVM
• Ability to work independently and drive projects to completion
• Experience in IP development, particularly in DFD IP (desirable)
• Excellent problem-solving and communication skills
• Knowledge of C++ (desirable)
• Familiarity with bus protocols like AXI, CHI (advantageous)

Join Tenstorrent and be part of a team revolutionizing AI technology and pushing the boundaries of computing performance.