Sr. DFT Engineer
Description For Sr. DFT Engineer
Tesla's Silicon Development Group is seeking a Senior DFT (Design for Testability) Engineer to join their innovative team working on custom ASIC design-to-production. This role is crucial for developing and implementing state-of-the-art testability, debug, and safety features for Tesla's custom silicon solutions.
As a Sr. DFT Engineer, you'll be at the forefront of ensuring high test coverage, quality, and safety standards while optimizing test costs for Tesla's automotive silicon solutions. You'll work with cutting-edge technology and collaborate with cross-functional teams including physical design, test engineering, and product engineering.
The ideal candidate will bring deep expertise in testability techniques, JTAG protocols, and ATPG, combined with strong programming skills in Verilog, TCL, and Python. You'll have the opportunity to work on complex challenges in silicon development while contributing to Tesla's mission of accelerating the world's transition to sustainable energy.
Tesla offers an exceptional benefits package including comprehensive healthcare, 401(k) with employer match, stock purchase options, and various family-friendly benefits. Located in Austin, you'll be part of Tesla's growing presence in Texas, working on technology that directly impacts the future of electric vehicles and sustainable energy solutions.
This role offers an exciting opportunity to work with world-class engineers, tackle complex technical challenges, and make a significant impact on Tesla's silicon development initiatives. Join Tesla's Silicon Development Group and be part of shaping the future of automotive technology and sustainable energy solutions.
Responsibilities For Sr. DFT Engineer
- Define and implement various DFT features at RTL and gates using in-house flows
- Work closely with the physical design team in achieving design closure with DFT features
- Perform block-level scan insertion, ATPG, coverage analysis, and simulations
- Run top-level test pattern retargeting and simulations
- Identify design changes needed for improving test coverage
- Work with test/product engineering team members on test pattern delivery and Si bring up
Requirements For Sr. DFT Engineer
- Knowledge of Testability techniques and features (Compressed Scan, Built-in-Self-Test, Loop-Back, Boundary Scan)
- Well versed in JTAG/1500/1687 networks
- Expertise in ATPG, coverage analysis, and pattern simulations
- Good knowledge of Verilog, logic design, circuit design fundamentals and timing
- Working knowledge of TCL, python (or another scripting language like Perl)
- Degree in Computer Engineering or Electrical Engineering or equivalent experience
Benefits For Sr. DFT Engineer
- Aetna PPO and HSA plans with $0 payroll deduction
- Family-building, fertility, adoption and surrogacy benefits
- Dental and vision plans with $0 paycheck contribution
- Company Paid HSA Contribution
- Healthcare and Dependent Care Flexible Spending Accounts
- 401(k) with employer match
- Employee Stock Purchase Plans
- Company paid Basic Life, AD&D, short-term and long-term disability insurance
- Employee Assistance Program
- Sick and Vacation time
- Back-up childcare and parenting support
- Commuter benefits
- Employee discounts and perks program
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